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-- Company: 
-- Engineer:
--
-- Create Date:   22:26:00 12/07/2010
-- Design Name:   
-- Module Name:   D:/mis_docs/fpga/multiPB/sin_mutex/ise/multipb_smx/testb.vhd
-- Project Name:  multipb_smx
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: multipb_top
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY testb IS
END testb;
 
ARCHITECTURE behavior OF testb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT multipb_top
    PORT(
         clk_50 : IN  std_logic;
         rst : IN  std_logic;
         switches : IN  std_logic_vector(3 downto 0);
         leds : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk_50 : std_logic := '0';
   signal rst : std_logic := '0';
   signal switches : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal leds : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_50_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: multipb_top PORT MAP (
          clk_50 => clk_50,
          rst => rst,
          switches => switches,
          leds => leds
        );

   -- Clock process definitions
   clk_50_process :process
   begin
		clk_50 <= '0';
		wait for clk_50_period/2;
		clk_50 <= '1';
		wait for clk_50_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
		rst <= '1';
      wait for clk_50_period*500;	
		rst <= '0';

      wait for clk_50_period*10000;
		switches <= "0001";
      wait for clk_50_period*10000;
		switches <= "0010";
      wait for clk_50_period*10000;
		switches <= "0100";
      wait for clk_50_period*10000;
		switches <= "1000";
      wait for clk_50_period*10000;
		switches <= "1111";

      -- insert stimulus here 

      wait;
   end process;

END;
